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Using Pspice to analyze amplifier loop stability (Part 2 of 2)

(Part 1 looked at what makes an amplifier unstable, and worked through a high-speed low-noise transimpedance amplifier (TIA) stability example.)

Practical considerations and bench results comparison

Armed with a good Pspice based analytical method to investigate proper compensation and having found the value which simulates to give the best response, the next step is to verify the simulation results on the bench. Figure 9 is a setup used for bench verification.

Figure 9 : TIA Compensation Bench Verification Setup

Here are some comments about the bench setup shown in Figure 9:

a) Low Value Capacitance & Bench Optimization: It is possible to use the RA , RB combination next to CF in order to reduce its effective capacitance. This is done so to use a readily available capacitance (>1pF) to look like a sub-pico Farad value, which is harder to obtain. The arrangement reduces CF ’s equivalent capacitance by a factor of 1+ RB / RA as long as RB << RF . The combination shown here results in an equivalent capacitance of 0.20pF and was chosen because the simulation value of 0.25pF resulted in an overdamped bench response. The physical board has some parasitic L and C which can be minimized but cannot be reduced to exactly 0. Thus, it is to be expected that bench measurements are leveraged to optimize the simulation findings, especially when dealing with sub-pico nominal values. Measured bandwidth drops to 55MHz with 0.25pF equivalent capacitance, vs. 70MHz with 0.20pF.

b) Equivalent Photodiode Bench Setup: The front-end configuration shown (Rin, Cin, and CD) allows the use of standard 50 W lab equipment to mimic the behavior of a photodiode for testing purposes. Here CD is set to 10pF which is the assumed photodiode capacitance.

Figure 10 and Figure 11 show the resulting frequency and step responses respectively using 50 W source and load termination at the output. As can be seen, the -3dB bandwidth is close to 70MHz with no peaking. The step response plot rise and fall times match the frequency response bandwidth and show minimal overshoot and no ringing to confirm that the circuit is proper compensated. For further verification of the simulation observances, bench testing confirmed large peaking with no compensation capacitor and full blown oscillations with 10pF directly across RF .

 

Figure 10 : Measured Frequency Response with CF _equivalent = 0.2pF

 

Figure 11 : Measured Step Response with CF _equivalent= 0.2pF

It is reassuring to also mention that the resulting, properly compensated measured bandwidth of ~70MHz matches well with the theoretical expression in Equation 1 with CIN being the total inverting input capacitance (diode and Op Amp both).

 

Equation 1 : TIA Theoretical Bandwidth

This example demonstrated the flexibility and ease with which one could investigate loop stability by opening the loop and using Pspice’s iterative functionality (the .STEP function) to simplify looking for an optimum compensation in a fraction of time needed and with greater insight. The Op Amp Macromodel used for this must accurately model the device (including the input stage parasitics), or otherwise the results obtained may be far from actual. The technique demonstrated in this example is not unique to the TIA circuit (which was chosen as a representative example) and can be applied to most amplifier circuits.

About the author

Hooman Hashem i is an application engineer who joined National Semiconductor Corp in 1995. He has an MSEE from Santa Clara University (1989) and a BSEE from San Jose State University (1983). He currently works in National's High Speed Signal Path group.

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