Variability in Small Geometries Can Cause Unexpected Problems

There is a constant drive for greater levels of integration these days. Being able to put more parts of a system on a single chip results in lower total costs, increases the options for design packaging, improves performance, and a host of other positives. In most cases that means that analog capabilities have to be integrated with the digital pieces and the digital pieces will likely be using the very latest technology nodes. Currently, the most complex designs being used in smartphones are manufactured at 28nm. Each new node generally enables double the number of digital gates to be packed on a chip.

However, these smaller nodes create problems for analog circuitry and additional complexity of design. In a nutshell, transistors suffer from an increase in uncertainty. In addition, new concerns come to the fore such as reliability caused by electromigration. Layout-dependent effects have become increasingly problematic and in this blog I am going to talk about a few of those effects and how they can be used for our advantage.

Layout-dependent effects are a result of how a layout is realized. Examples of the realizations include the distance a device is from a well or the distance between active regions. Conditions such as these can affect the characteristics of a transistor, including mobility and threshold voltage. Now the effects I am talking about are not small — they can be between 20 percent and 80 percent and can therefore play a significant role in the performance of the circuit. The two most prominent effects are shallow trench isolation (STI) and well proximity effects (WPE).

Let's start with STI. A trench creates stress in silicon caused by mismatched thermal properties between the two materials. Stress has been used in previous nodes to improve transistor performance. A tensile stress (pulling) improves NMOS devices and a compressive (pushing) stress improves PMOS devices. Tensile stress increases electron mobility and compressive stress improves hole mobility — each increasing current flow in the corresponding devices.

The good news is that these stresses are controllable by varying the length of the diffusion (LOD) region under a device. As LOD decreases, the compressive stress increases and this is beneficial to the PMOS transistors, but degrades NMOS transistors. As a PMOS transistor gets closer to a STI edge, threshold voltage decreases and current increases. By increasing the size of the STI region, the stress can be increased.

Related to STI is the second source of variability — WPE. This relates to the location of transistors with respect to the well boundaries. For PMOS, WPE results from enclosure of a well around the transistor and for NMOS it results from the distance of the transistor from the well. This is caused by atoms scattering off the mask during high energy implantation stages used to create deep buried layers. As the distance from the edge increases, the concentration of embedded atoms decreases. The location of the device with respect to the well affects mobility and threshold voltage.

Neither of these effects can be accurately captured during circuit design because they are so dependent on the physical implementation details, meaning that some level of experience in these effects needs to be considered when defining the circuit. Without this knowledge, large and problematic iteration loops may be seen. To demonstrate how significant these can be, consider the diagram below. This comes from the book Mixed-Signal Methodology Guide written by Cadence.

The diagram shows the sensitivity to well distance in a standard amplifier circuit. The analysis shows the gain variation of the circuit as the distance to the well for one of the transistors in the first stage is swept.

(Source: Cadence)

(Source: Cadence)

What other physical effects are you aware of that analog designers should be taking into account when using smaller geometries?

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1 comment on “Variability in Small Geometries Can Cause Unexpected Problems

  1. Steve Taranovich
    September 30, 2013

    Nice article Brian,

    In the paper, “CMOS Op-amp Circuit Synthesis with Geometric Programming Models
    for Layout-Dependent Effects” by The University of Kitakyushu, the authors examine the transistor sizing in the CMOS analog circuit, and provide the posynomial forms of the circuit specification taking into account coping with the short channel effect.

    They examined the 90nm process and lower, for the short channel effect, and discuss the channel length modulation tendency to increase as the channel length becomes shorter.

    The transistor sizing is done by geometric programming (GP) which optimizes the circuit while using layout-dependent effect (LDE)-aware models.

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