Very Low Gate Threshold FET – Maybe Too Low?

I've designed with FETs since I was a kid. Several jobs ago, I used lots of depletion mode N-channel JFETs as the heart of a flame detector in some gas ignition and control devices we manufactured. Those took advantage of the slight rectification ability due to the ionization process in a burning flame. In a more recent job, I used enhancement mode N- and P-channel MOSFETs on various power and signal control circuits.

I mention all this as background. I received a press release from Advanced Linear Devices (ALD) that talked about their new precision dual N-channel MOSFET that is “precision matched at the factory” so I don't have to. I'm certainly in favor of that, having designed and built fixtures to match FETs and then tested and binned them.

This would be useful for differential input stages or as part of a current mirror, so being matched is absolutely what I'd want. But the other selling points had me scratching my head. One point said the device features “…high DC current gain (>108 ). A sample calculation of the DC current gain at a drain output current of 30mA and input current of 300pA at 25°C is 30mA/300pA = 100,000,000, which translates into a dynamic operating current range of about eight orders of magnitude.”

High current gain? This is an N-channel FET, not a BJT. It's a transconductance device — voltage input, current output. But wait — the gate threshold voltage “features Zero-Threshold voltage.” Hmm… I suppose that would make it a good part to use for very low-voltage circuits, except that with a zero voltage threshold, how do you know if it's on or off?

The graph from the data sheet confirms that the threshold is right around zero. The likely thing that's done in the FET processing to make this happen is (probably) making the conduction channel (drain to source) very narrow, and making the gate oxide (insulating) layer super thin. Which makes it prone to leakage. Which would mean you'd get gate current flow. Aha! That's why they have that parameter (above) that makes it look like it has a beta of a hundred-million.

And with such a low threshold voltage, they can claim that “…a circuit with multiple cascading stages can be built to operate at extremely low supply/bias voltage levels. For example, a nanopower input amplifier stage operating at <0.2V supply voltage has been successfully built." I suppose so, but how do you turn it off?

My mistake here is assuming the device is simply a conventional enhancement mode FET. It's not quite that. Nor is it exactly a depletion mode. It's right in the middle. You'd need to bias the gate just a little negative to make sure it's off. And you'd only need to bias the gate just tens of millivolts positive to make sure it's on. So this would be dandy for energy harvesting circuits (about which we've written before). Amplifier circuitry for sensors, ultra-low power boost switchers, some logic circuits, or circuits where the FET should be “normally on” would benefit.

We'll do some more research on these parts and let you know what we learn. And please let us know if you have applications that could use a device like this.

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14 comments on “Very Low Gate Threshold FET – Maybe Too Low?

  1. amrutah
    June 29, 2013

    Instead of channel dopant a very thin tox… Low Vt device is almost a near depletion device.

      These can be very helpful in always on circuits like oscillators, reference system.

    These devices can be used in series (or cascode) with High Vt device used for power gating to reduce leakage during off period.

  2. amrutah
    June 29, 2013


      Thanks for sharing this very interesting.

       Is the tox made of high-K dielectric, how does it sustain the high electric field in the gate region?

       Any more information about the device construction?

  3. Scott Elder
    June 29, 2013

    If one needs a current bias to startup a circuit where the supply voltage can have a large range, Vt=0 MOSFETs are very useful.  Simply short the gate to source and tie to ground.

    They operate like a resistor except the amount of current they provide is limited once the drain voltage is slightly positive (i.e. as the power supply comes up).  During power down the device looks like a pull down resistor to keep the supply low.  During power up, the pull down becomes a limited current at a low value.

    In the days where analog ICs were primarily bipolar, JFETs served this purpose.  Eliminates the need for a huge integrated resistor (i.e. 10 Megaohm).


  4. D Feucht
    June 29, 2013

    “A sample calculation of the DC current gain at a drain output current of 30mA and input current of 300pA at 25°C is 30mA/300pA = 100,000,000, which translates into a dynamic operating current range of about eight orders of magnitude.”

    That is what I thought at first too, but because the parameter is meant to be dynamic, this might be incremental current gain with some reference resistance, gate to source. But I'm just guessing. Otherwise, I'm perplexed too.

    @ Scott – very astute observation. I am using a JFET in a “Floating Differential Source” to sink (into a positive output source) bias currents from translator circuits – the kind of thing that happens when multiple floating sources exist in the same circuit environment. And to sink the current of 4 to 8 mA, I am using a JFET configured as you describe. However, low-IDSS JFETs are now hard to find. So this part might have a good purpose.

  5. David Maciel Silva
    June 30, 2013

    Due to inrush current of this device is very low, we can use in drive applications, mainly for switching circuits powered by batteries.

    What do you think?

  6. Brad Albing
    June 30, 2013

    I do have access to more info – let me see if I can get one of the AMD guys to comment. Stand by.

  7. Brad Albing
    June 30, 2013

    I think it does indeed lend itself to use in battery operated devices. Lots of possibilities here.

  8. SunitaT
    June 30, 2013

    @Brad, thanks for the post. Interesting to learn about FET which is neither  enhancement mode FET nor depletion mode FET. Eagerly looking forward for outcome of your research on this product.

  9. SunitaT
    June 30, 2013

    These devices can be used in series (or cascode) with High Vt device used for power gating to reduce leakage during off period.

    @amrutah, interesting idea. I agree with your suggestion putting this device which has high leakage in series with thigh Vt device definitely helps us to reduce leakage during off period. I am curious to know if such architecture is commonly preferred in the designs ?

  10. amrutah
    June 30, 2013


       I have read papers where there are twin well process and low voltage to support, there are designs where the circuit can operate at low as 0.3V ( for 45nm process nodes). Check this

     But the critical factor is we are on the verge of 0 volts and to turn off we need to go below 0V.

  11. Brad Albing
    June 30, 2013

    @amrutah – exactly my point – it's helpful to have a device with very low turn-on threshold – but not too low, or you'll need a negative voltage to insure it's turned-off. So it starts to look like a depletion mode part. Still, I'm glad to see someone is making these devices.

  12. SunitaT
    June 30, 2013

    But the critical factor is we are on the verge of 0 volts and to turn off we need to go below 0V.

    @amrutah, yes I agree with you. Switching off the FET by giving voltage which is less than 0V is critical. Is it better to have device which require negative voltage to switch off or is it preferrable to have device which turns on when we give +ve voltage ?

  13. amrutah
    June 30, 2013


       In case of CMOS circuits. then you will have to build negative charge pumps t generate the negative supply and then use them to bias these devices. Negative charge pumps are a monster in themselves to handle…

  14. RedDerek
    July 3, 2013

    I will need to look at the data sheet. I see some interesting applications as well. As for construction, it looks to be that middle-of-the-road device between the enhancement and depletion MOSFET. I looked years ago about using MOSFETs as a current mirror, but matching two devices would be very difficult, obviously I would not be looking at a 0 Vgs device then. But to match, the best method, as shown, is to co-package. This way the semi manfucturer can grab adjacent die off the wafer to help ensure the match. MOSFET characteristics will shift from lot to lot, and from wafer to wafer within the same lot. And there is even a shift from one side of the wafer to the other. But if one can get die that are located next to eachother on the wafer, one is sure to get a matched pair.

    The space program that needed good current mirrors would pay a premium for number sequenced BJT devices so that they know that part xxxx and part xxxx±1 will match each other. Just not sure how they knew when the next sequenced number means the start of a new row of parts on the wafer.

    Oh, as for application, I can see this would be great for driving LED strings. With matched FETs, the focus would be Rds*Id loss, yet be able to have one string have the same current as the next. Trick is that if one has multiple strings, say 4 and 5 or more, the 2 FET package would not be much help – I would look at a quad-packed part; but the Vth would be higher compared to this one.

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