A video recorder on a chip (comparable to the audio recorders on a chip but more complex, of course) would be a useful device. Even more useful would be a very low-power video recorder on a chip. You could build it into the frame of your glasses or the visor of your baseball cap. If the power were sufficiently low, operation from a single cell might be practical.
This seems like the sort of technology that appears in Star Trek movies, but such a device will likely be available soon as a system on a chip (SoC). In a recent paper presented by the IEEE International Solid-State Circuits Conference (registration required), a group of engineers present such an IC in prototype form. The IC features a very low-power microprocessor unit, very low-power ROM and RAM, provisions for an external memory interface (everyone always wants to add memory), provisions for external camera and LCD interface, and an H.264 video encoder. H.264 is a very common standard for video compression.
The prototype device was fabricated on a 65nm process. Recordings can be made at 32 frames per second in HD720 high definition. At reduced power levels (battery voltage at 0.48V), recordings can still be made at 30fps. At this point, energy consumption is estimated at 0.57nJ/pixel.
The design engineers tell us in their paper that they used various techniques — analog, digital, and software related — to get the desired performance and power consumption.
Energy efficiency has been improved through algorithm, architecture, and circuit techniques. At the algorithm level, a complexity and bandwidth-effective group of macroblock (GOMB)-based motion estimation (ME) with adaptive search range (ASR) is proposed. The bandwidth is reduced by ~71% at a negligible cost of 0.1dB quality loss as compared with the full-search ME in the H.264 reference software.
At the architecture level, a low-latency in-loop filter output buffer (ILFOB) and a block-based current/reference frame buffer (FB) organization are designed to reduce by 69% the number of cycles for external DRAM access. Combining these algorithmic and architectural techniques can reduce bandwidth by ~81% in total. Furthermore, ultra-low voltage circuit-level techniques… provide a ~70% energy reduction compared with a state-of-the-art H.264 encoder design.
To see how the designers have squeezed all this functionality into such a small space (approximately 4mm square), let's look at the block diagram:
Here is more detail on the H.264 video encode — both the architecture and the associated algorithm (click here for a larger version).
The authors provide more details on what their FB implementation does and why it's an improvement over other versions.
A 512Kb FB is included in the video-recording SoC for the H.264 encoder to store prediction data and macro-blocks from the reference frame. Compared with the state-of-the-art ULV SRAM design of 256Kb, our 512Kb FB halves the bitline (BL) loading (from 512b/BL to 256b/BL) to improve both the performance and the power dissipation.
Power draw at 1.0V VDD supply is 2.68mW — not especially impressive. Much of the power draw is due to leakage currents. This occurs with process technology this small. When operating at a VDD of 0.48V (the minimum operating voltage), power draw drops to an impressive 312μW
Here's a look at the die.
Have you worked on any video devices for HD applications? Anything at these power levels?