In the first part of this blog, Virtual Eval Through the Eyes of an ADC, we had an introduction to Virtual Eval which is the new online simulator tool offered by Analog Devices. My desire with the first installment was to introduce the tool with a less complex ADC for an example so we could get a handle on the features of the tool before diving into a more complex ADC with additional digital signal processing features. Now that we’ve had a chance to learn a bit about the tool we will take a look at using Virtual Eval to predict the performance of the AD9680-500 which has integrated digital downconverters (DDCs) and will compare simulated data to measured data.
Once again, the first step is to open the tool from the website and select an ADC to simulate. The tool is on the Analog Devices website at Virtual Eval as we discussed in part one. For the purposes of this blog I am going to point you once again to the AD9680 which incorporates a new feature being developed which allows the user to simulate different speed grades of ADCs. This feature is key to our example since we will be looking at the AD9680-500.
Product Category Selection Page in Virtual Eval
Once we select the AD9680 from the product selection it will open up the main page for the simulation of the AD9680. Notice that there is a block diagram shown that gives details on the internal configuration of the ADC analog and digital features. This block diagram is the same as the one given in the data sheet for the AD9680. From this page we need to select the desired speed grade from the drop down menu on the left side of the page. In this case we will select the 500 MHz speed grade.
AD9680 Speed Grade Selection in Virtual Eval
Next the input conditions must be set in order to perform the FFT simulation. For this example the clock rate is set to 491.52 MHz and the input frequency is set to 150 MHz. The DDC is enabled with the NCO frequency set to 155 MHz, the ADC input is set to Real, the complex to real conversion (C2R) is disabled, the DDC decimation rate is set to four, and the 6 dB gain in the DDC is enabled. This means the DDC is set up for a real input signal and a complex output signal with a decimation ratio of four. The 6 dB gain in the DDC is enabled in order to compensate for the 6 dB loss due to the mixing process in the DDC. Once again I am showing two plots so that the noise and distortion results can be viewed.
AD9680 FFT Simulation in Virtual Eval – Noise Results
AD9680 FFT Simulation in Virtual Eval – Distortion Results
Notice all the nice things that the Virtual Eval tool will point out. You can see that the tool denotes the harmonic locations as well as the image of the fundamental. I find the marking of the fundamental image to be quite handy. I have personally seen many questions relating to spurs in the output spectrum which I have discussed in my previous blogs. Virtual Eval makes frequency planning a bit easier by allowing the user to see if the fundamental image or any harmonic tones show up in the desired output spectrum. Virtual Eval reports that the expected SNR is 71.953 dBFS and the expected SFDR is 69.165 dBc. Let’s consider for a moment however, that the fundamental image would not typically be in the output spectrum and if we remove that spur then the SFDR is 89.978 dB (which is 88.978 dBc when referred to the -1 dBFS input power).
Now let’s refer back to the measured data that I showed in my previous blog ADC Digital Downconverter: A Complex Decimation Example Revisited. The measured results show something a bit interesting. The SFDR given in the measured result is 65.625 dBc which is quite close to our simulated result in Virtual Eval of 69.165 dBc. However, notice something very interesting here though. The SNR value is significantly different! The measurement result shows that the SNR is 65.79 dBFS while the Virtual Eval simulation shows 71.953 dBFS.
AD9680 FFT Measurement Result
Where did all those dBs go??? Well, it turns out that they haven’t gone anywhere. I thought I’d test you as readers to see if you might catch the SNR calculation in VisualAnalog in my previous blogs. Did you see it before? This is something important to note when considering how the SNR calculation is performed in Visual Analog. The Virtual Eval simulator does not include the fundamental image when it calculates the SNR. If we adjust the settings in Visual Analog to ignore the fundamental image in the measurement we achieve the correct SNR. Notice now that the SNR reported is 71.602 dBFS which is quite close to the simulated result of 71.953 dBFS in Virtual Eval. Also notice that the measured SFDR is 91.831 dBc which is also very close to the simulated result of 88.978 dBc.
AD9680 FFT Measurement Result – Fundamental Image Removed from Results
It is great to have a simulation tool that can accurately predict the behavior of hardware. Virtual Eval offers some very nice features to aid in system design without needing hardware to measure in the lab. The user can predict device behavior from the comfort of a nice chair at their desk. Particularly in the case of an ADC with DDCs such as the AD9680, it is very handy to be able to simulate and frequency plan such that undesired fundamental images and harmonics can be planned out of band where possible. Speaking of DDCs, if you’d like to learn more about the DDCs in the AD9680 make sure to check out my latest article in Analog Dialogue: What’s Up With Digital Downconverters Part 1. This article discusses the DDCs and offers some more insight into this example. It will help equip you to understand how to use the DDCs so you can then use Virtual Eval to help in your next design. With tools such as the Frequency Folding Tool, and Virtual Eval as well as many other simulator tools from ADI it enables designers to create system design solutions faster and easier. For links to these tools and more check out this website: Data Converter Tools. I encourage you to go check out these tools today and incorporate them into your next design.