Digital designers sign off on their designs' timing performance using a mix of dynamic (e.g., Verilog simulation) and static (e.g., PrimeTime) tools, then hand off the design to manufacturing. In the system-on-chip (SoC) era, however, we have to ask whether this is all the verification that is needed to create a successful SoC design. Unfortunately, the answer is no.
That's because analog and mixed-signal (A/MS) circuitry requires a significant verification effort at the electrical level, even though it is only a fraction of the total device count for an SoC. If we don't exhaustively perform A/MS verification, we end up with multiple respins trying to get the design right. If we do perform the extra verification using current methods, we can seriously delay the tapeout date. The result? The SoC gets to the target application late, and the end product misses its optimal market window.
What needs to be done to achieve signoff for the A/MS content in an SoC before tapeout to manufacture? Verification is challenging enough for the current generation of A/MS circuits, which have grown dramatically in speed, functions and transistor count. The challenge is even more difficult as various power modes are used in portable designs. The latest nanometer silicon technologies have poorer signal-to-noise (S/N) performance and more variability in the analog transistors. The current design and verification tools, while suited for small analog blocks, are severely strained by the requirements of these complex A/MS circuits.
Unlike today's large digital designs, for which separate teams do design coding and verification, A/MS designers build and test their own circuits before handing them off for integration with the rest of the SoC. This traditional approach involves too much manual effort by the A/MS designer.. For the analog electrical block found in a high-speed serial interface such PCI Express, the specification for jitter behavior can be a hundred pages. It is a daunting task to translate this into the right set of test measurements for a typical Spice simulator. Besides writing the correct tests, the designer needs to run them across all the process corners, voltages, temperatures and operating modes for the circuit. Typically, the tests are simulator- and design-specific and are not portable to future projects or different design teams.
Given that the analog portion of the design is often the most risky in terms of success for the entire part-and that the complexity challenge is growing-analog/mixed-signal designers need a new testing approach.
Exhaustive testing should be done before tapeout, and more A/MS simulation must automated to virtually eliminate manual methods. Analog testbench automation can help. For parts or circuits implementing industry-standard protocols or specifications, using an off-the-shelf analog testbench would significantly reduce the burden of test creation and would give early feedback on how a circuit is meeting the design goals. Because testbench automation can be independent of any particular circuit and simulator, it allows reuse for the next project or by different design teams. To achieve timely simulation results, more Spice and fast-Spice licenses must be made available to design teams to eliminate the bottleneck in achieving exhaustive test coverage.
With a rigorous and automated methodology, A/MS signoff can be achieved if design teams say “yes” to using the latest testbench and simulation technologies and move beyond traditional approaches. Now, the question becomes, how do we change the fundamental manual orientation of current A/MS design and verification?
About the author
Sandipan Bhanot is the president and CEO of Knowlent Corp. He has a 16-year track record in the EDA industry in various engineering, marketing and sales management roles. Bhanot holds an MBA from the Haas School of Business at UC Berkeley and a BS in computer science from the Institute of Technology in Varanasi, India.