What Happened to Napkin Sessions?

What happened to the days when designers of analog blocks would sit around and chat over a lunch break or time away from the pressures of work and design on napkins?

The idea of a napkin session is for designers to scratch out designs and circuits on paper and design with a paper and pencil before even contemplating placing the circuit into the simulation environment. I believe this method of design is not followed as rigorously by many of the engineers as was the case in the past on the larger scale technologies. Granted, the tools available at an engineer's disposal allow for a plethora of simulation cases to design a circuit. However, there is a problem with this type of design. The engineer disengages the brain. I know this may irritate some of those that read this article, but let me restate the issue.

I am sure many of you have seen or heard of George Jetson. In this cartoon land, George's job at work is to push a button and the computers take over. The work of the company is placed into the decision matrix and “smarts” of the computer. What an ideal life. You push a button and your job is finished. Heck, you now have time to golf, read a book, or whatever else suits your fancy. Does this really work for analog design? I am sure as tools and algorithms become more sophisticated, at some point in time the design engineer may be able to reliably design circuits by pushing the proverbial button (or simulation optimizer in this case). But until that time in the future, there is danger in relying on computers to do the thinking. As the old saying goes, garbage in equals garbage out. This is why we need to return to the idea of the napkin sessions.

Napkin sessions allowed for engineers to design analog blocks on paper and explore tradeoffs on paper using rudimentary hand calculations. As further emphasis of this need, I quote in an article from Yannis Tsividis1 , “some people lacking design experience do not appreciate how valuable this is.” This use of hand calculations quickly allowed engineers to understand tradeoffs in the design space. In addition, by understanding the sensitivities and functions of the blocks from a mathematical perspective, the designer can avoid designing and optimizing in a sub optimal design space — often an evil that plagues designers from many companies. See Figure 1.

Figure 1: A typical napkin session records brain-storming ideas during an informal meeting atmosphere.

I know that there is the tendency and pressure to finish a design quickly. This often leads to the evil of simulating without knowing what design space is best. If this starts to happen, push back and resist the tendency. It is OK to ask for more time to implement a quality design in lieu of a quick design. The quick design may cost more in the long run because your design is sensitive to process corners that often lead to more area and power. Remember, once the area is allocated for analog blocks inside a system on a chip, reducing the analog area later after a production mask is developed, does not often translate to a reduction of area for SOC without significant layout work — you're stuck, so do it right the first time.

So, if you think about carrying out a napkin session, the first question that may come up is whether or not the first order fundamental hand calculations are adequate? For smaller geometry technologies, I would argue that a first order equation may be inadequate. So what do you do? To answer this question, we need to have a tool that allows for back of the envelope type calculations. This is a possibility.

The tools needed for back of the envelope calculations to enable napkin sessions is available at some companies but should be made available at all companies designing analog blocks. The idea would be to have simple circuit blocks that run off actual simulation models that allow for information that can be used in the fundamental first order equations used for back of the envelope calculations such as unity gain bandwidth, mismatch, rout, etc. A tool that allows for such calculations may include basic building blocks such as differential pairs, current mirrors, and voltage driven devices as shown in Figure 2. For further information, please reference the following paper written in 2006 “A Web Tool for Interactive Exploration of Analog Design Tradeoffs.”2

The use of a tool such as the web-based tool referenced allows the designer to quickly understand tradeoffs for various performance parameters such as amplifier bandwidth, offset voltage, noise, output swing, etc. To gain a better understanding of this idea, I would like to explore the calculation of the input offset voltage of a simple amplifier. Please note, that although I am referring to the calculation of the input offset, I could have easily also calculated the input referred noise as both measured values are dominated by the input stage gain — please reference “A Web Tool for Interactive Exploration of Analog Design Tradeoffs” for more detail on the input referred noise.

As previously stated, the input offset voltage of an amplifier is usually dominated by the gain and offset voltage of the differential pair and the load of the differential pair. Shown in Figure 3 is a simple configuration of the first stage of a generic amplifier that could be programmed into a tool for exploring the input offset voltage of the amplifier for various device sizes and currents.

To calculate the device parameters that contribute to the total input offset voltage can be tedious and often incorrect. This is especially true when the closed form expressions in the sub micron geometries for threshold voltage, mobility, L and W do not match traditional long-channel device characteristics. Thus, there is the need to allow for calculation of these parameters to enable hand calculations of the desired performance parameters such as input offset voltage in the example. The calculations for a performance parameter such as input offset voltage involves the calculation of the offset currents of the load devices as well as the offset voltage of the differential pair.

The calculations require the derivation of the mismatch load current and offset voltage of the differential pair that are functions of the various process transistor parameters. As referenced in “Understanding MOSFET Mismatch for Analog Design” the variations of device parameters such a current mismatch or offset voltage is composed of a propagation of variances where the total variations for a parameter such as current mismatch are composed of variances of several process parameters including ΔW, ΔL, ΔVfb, Δtox , Δµ, ΔL, ΔNsub , etc. The sum of these various process dependent variations provide the information desired to assess the statistical properties of any electrical parameter that for the example mentioned is either the variance of IL or Vos.

As was shown in the reference, the variance of any electrical parameter “e” and a process parameter “i” is given by:

These process variations are used to provide the design parameters needed for the hand calculations. Because the derivation involves the calculations of partial derivatives due to local variations, the time involved is extensive and often the results could be inaccurate and cause errors in the hand calculations. Therefore, these types of calculations are perfect for using a tool that runs simple simulations based on the technology to come up with the various process dependent design parameters.

The outputs from a tool such as previously referenced, provides information on the variation of the current IL as well as the variation in Vos. These provided parameters enable the designer to easily combine the results to provide a composite offset voltage given by equation #1. Note that this example demonstrates some of the complexities of calculating the parameters needed for use in the hand calculations. In addition, performance parameters such as transconductance, rout, Fτ ,and vdsat provided from simple sims of the technology, enable the designer to calculate performance objectives such as:

By using the technology specific models, the designer can obtain accurate device parameters such as transconductance and output conductance to enable the hand calculations of these types of performance parameters. The beauty is that the designer can obtain trends of the design from these simple calculations and optimize over various performance parameters simultaneously.

The errors associated with using a simple calculation such as the input offset voltage are often insignificant once accurate values for the technology specific process parameters are available to the designer. The point is that understanding the trends from these simple hand calculated performance parameters, the designer can potentially avoid the pitfalls of designing in a suboptimal design space that may cost extra power, area, time, and future headaches.

The methodology of designing by utilizing tools to extract the process dependent device parameters enables the ability in newer sub-micron technologies and older technologies to extract simple numerical values used for back of the envelope calculations. This method facilitates an environment for the designer to engage early in the design process by using the idea of a “pencil and paper.”

Furthermore, the use of hand calculations enables the engineer to understand how the circuit being designed really works and the sensitivities that lie therein. Until the algorithms for optimization becomes reliable, the design engineer must be able to spend some time upfront understanding the circuit being designed before the plethora of simulations start. The cost for not using the idea of a napkin session can be costly to the company in lost profits, time, and possibly future opportunities.

Let me know what you think. Do you agree with these statements? Have you seen loss of time and revenue from circuits that were designed using the George Jetson method of design?


  1. IEEE Solid-State Circuits Magazine, Winter 2014, Vol.6 No.1, Page 38
  2. “A Web Tool for Interactive Exploration of Analog Design Tradeoffs,” Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
  3. “Understanding MOSFET Mismatch for Analog Design,” IEEE Journal Of Solid-State Circuits, vol. 38, no. 3, March 2003

18 comments on “What Happened to Napkin Sessions?

  1. Davidled
    March 18, 2014

    In most time, during engineering meeting, there is some discussion among engineer. They would express their idea and design concept on white board. Then, smart phone camera will take this picture. Then all information will sent by email.    

  2. samicksha
    March 18, 2014

    In my opinion most of the engineers have their own idea, again either with pencil and paper or marker and board. The concept of Design your own circuit sounds good but only when design yield expected and proven results. Also urgency and pressure of constructing design sometimes creates gap and flaws which later becomes problem.

  3. Netcrawl
    March 20, 2014

    @samicksha I agree with you pressure, its true it create problem, we all know the pressure of deadline, the closer they get the more pressure there is and the more trouble we get- its a like race. 

  4. Netcrawl
    March 20, 2014

    In some companies they have this “brainstorming things”, I believe it all start on a simple idea and meeting, they use whiteborads and presentations to express their design and ideas. And then comes some talks and debate about the plan.  

  5. jlwayt
    March 20, 2014

    Hi Brandt, I like how the thought began on the “ancient practice” of the napkin session but I feel you blew it and drifted off topic. The idea of a couple or group of engineers sitting down together in a relaxed environment away from the normal office distractions and kicking around a design is truly lost today, but not because simulation is the faster route to a completed design. It's a way of getting more than just a single brain working on an idea. If one person can single-handedly juggle every variable in a desigh then they're the grand exception. I'm of the opinion that the more the merrier kicking around the beginnings of a design leads to a more robust end product. The group can leverage the knowledge and experience of all of it's members from past experiences and educational differences to work through the variables, decide which ones need to be carefully examined and which ones can be ignored based upon the end goal. Reliance on simulation to achieve this relies on teh programmer to have considered ALL possible variables and events and to have crafted calculations that cover every possibility and achieve the correct outcome despite never having heard the design requirements. This is not what I've experienced with simulation.

    I feel the bigger issue may be that the older generations of engineers have grown up discussing designs and are more comfortable in general working as a group whereas the younger generation of engineers are more reliant on electronic forms of communication and  computers and are less likely want to seek out other opinions, relying instead on the software to figure it out and spit out the answer. I have witnessed first hand the generational split in engineering departments where the older engineers get together to swap war stories and ideas and the younger engineers avoid these impromptu gatherings in favor of email, texting and the Web. I have also witnessed more bad designs from the single-person efforts, mostly from flaws that would have been easily caught had the designer just conferred with another engineer just as a sanity check.  It's not entirely their fault. The reliance on computer simulation at colleges and universities over actual hands-on lab time is at least partially to blame. Labs are expensive to maintain and keeping up with the latest in test equipment, development tools, software and tooling can wreak havoc on a budget leaving simulation as the more economical route to take. You lose the interraction between students working on lab projects, the collaboration and groupthink that leads to the bonding of the design team and the impetus driving the napkin session once they're out in the workplace.

    If you ask me, I'll take a pen and napkin and good conversation over hours in front of a monitor any day.


  6. samicksha
    March 21, 2014

    I agree with your thought on Genaration gap but more than this i would say it's competition which is enforcing them to come up with best and stable design and in this race they miss out the basic aspects which later turn to flaw.

  7. amrutah
    March 22, 2014

    @samicksha, @netcrawl: I agree with you here.  Another important thing is, the IP re-use.  When you see some problem with the design even by calculations, it is often not changed as the expected results (off course observed and measured with the eda tools) meet the application spec.

  8. Vishal Prajapati
    March 23, 2014

    If I talk about my experience and my colleagues, we do design analog circuits but in the simulator first. Never thought about the topology and equations on paper first. I just open the simulator and put the parts adjust the values and see the result. If things doesn't work out, we start tweaking values and topologies. It is most of the time trial and error trick. We do discuss the ckts after that to make ckts better.


    Thinking it manually and tweaking it in mind is very hard. So, we never do nepkin sessions.

  9. RedDerek
    March 23, 2014


    I agree that a good brainstorming session in a relaxed environment could be more useful than hours in front of a computer. The napkin session can break the large problem down to small and managable sections. And those sections can be broken down further until basic circuit blocks can be sketeched out. The equations can then start to be dropped and basic calculations can be figured out.

    Jumping to a simulator next helps speed the details out, so long as the data coming out makes sense.

  10. geek
    March 27, 2014

    “, I believe it all start on a simple idea and meeting, they use whiteborads and presentations to express their design and ideas”

    @Netcrawl: That's one of the best ways to come up with creative solutions. Leave the space open and start with anything, and then build on the ideas. The IT industry is famous for following this approach but I'm not sure if a lot of engineering companies also do that. Engineers like to stick to traditional approaches from what I've seen.

  11. geek
    March 27, 2014

    “I agree that a good brainstorming session in a relaxed environment could be more useful than hours in front of a computer. The napkin session can break the large problem down to small and managable sections”

    @RedDerek: Yea, that really works for me. Sometimes all you need is a change in the surroundings to make your creative thinking process works. Unfortunately, many companies may consider it a waste of time to let their designers go on a holiday and come up with something good during the process. It takes a while to change this thinking.

  12. Sachin
    March 31, 2014

    In theory, it is always better to take more time and come up with a quality design rather that rush to come up with a quick design but in practice the time pressures are a reality that we have to deal with everyday. So in as much as as the napkin sessions can help one create quality designs, the reality that we have tolive with favors computer simulations of every idea right from the start.

  13. Sachin
    March 31, 2014

    The computer simulations, important as they are, reduce creativity. Personally I don't understand how any engineer would fight the idea of napkin sessions, especially if he or she is into analog design. Sometimes an idea pops into your head and you put it down on paper and share with friends over the sessions if only to have an idea of what it would take to bring that to reality.

  14. yalanand
    March 31, 2014

    It is most of the time trial and error trick. We do discuss the ckts after that to make ckts better.

    @Vishal, many engineers follow such methods. They use automation tools to tweak the W/L and generate the output values and try to optimize the output value. But such trial and error methods can be used once the architecture is fixed. If architecture is not yet fixed then I think its better to start from equations on paper.

  15. Victor Lorenzo
    April 1, 2014

    @jlwayt >> The reliance on computer simulation at colleges and universities over actual hands-on lab time is at least partially to blame .

    I totally agree on that. I've had in front of me too many joung engineers (and unfortunately not too young too) who are totally incapable of differentiating transistors, SMD resistors and SMD capacitors from a bunch of components in a box. In this case I'm talking literally. Solder one 5x5mm 32 QFN package? Ooops!

    I should say that they do know how to use facebook, tweeter … 🙁


  16. Victor Lorenzo
    April 1, 2014

    @Vishal >> Never thought about the topology and equations on paper first .

    From my point of view and experience, an engineer which has a clear knowledge and understanding of the circuit and its operation principles, even when not having full formulae knowledge, is in a better position to succeed in the design and in finishing the task in a shorter time.

    >> I just open the simulator and put the parts adjust the values and see the result. If things doesn't work out, we start tweaking values and topologies. It is most of the time trial and error trick. We do discuss the ckts after that to make ckts better .

    That could sometimes work, but real life is too different from simulated life. One resistor-capacitor value pair could make the circuit exhibit the gain we need, but can also introduce instabilities at specific frequencies and create hard to debug analog dissasters.

    I learnt from older colleagues to start with a pre-design in paper which is very close to what I want to achieve. I use to fill several pages of hand drawings in my notesbook (yes, I have a notesbook with notes from many different projects).

    The simulator serves me for corroborating what I previously designed in paper with the help from a humble calculator and an excel worksheet.

    >> Thinking it manually and tweaking it in mind is very hard. So, we never do nepkin sessions .

    I had a couple of colleagues in a previous occupation that also liked to discuss about current projects, possible new projects and new ideas at lunch. It was common procedure for us to make notes on nepkins and also in the paper covering the table, then cut and take the piece of paper with us. That was a small but efficient part of the foundations for our success as R&D engineers at that time.

  17. Victor Lorenzo
    April 1, 2014

    @tzubair >> Sometimes all you need is a change in the surroundings to make your creative thinking process works .

    I had a colleague that was in charge of designing and producing the mechanical parts for machines we were designing. Some times I had really long design sessions with him trying to figure out how we could solve some specific problems. At the end he used to say, “let me have my pillow time this night…” and he always came up with a working solution next day. When relaxed, he was one of the most creative persons I've meet so far. He is now retired spending most of his time in his sail boat.

  18. yalanand
    April 30, 2014

    Napkin session is meant to be where the designers scratch out the designs and circuits on a paper and design with a pencil and paper before contemplating placing the circuit into the stimulation environment. This was used back in the 1980's and 90's by large-scale factories. That is not the case now. Everything has changed and scientists are coming up with new and faster ways to make and save their designs. It is basically a digital era. Science is taking over the world.

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