What happened to the days when designers of analog blocks would sit around and chat over a lunch break or time away from the pressures of work and design on napkins?
The idea of a napkin session is for designers to scratch out designs and circuits on paper and design with a paper and pencil before even contemplating placing the circuit into the simulation environment. I believe this method of design is not followed as rigorously by many of the engineers as was the case in the past on the larger scale technologies. Granted, the tools available at an engineer's disposal allow for a plethora of simulation cases to design a circuit. However, there is a problem with this type of design. The engineer disengages the brain. I know this may irritate some of those that read this article, but let me restate the issue.
I am sure many of you have seen or heard of George Jetson. In this cartoon land, George's job at work is to push a button and the computers take over. The work of the company is placed into the decision matrix and “smarts” of the computer. What an ideal life. You push a button and your job is finished. Heck, you now have time to golf, read a book, or whatever else suits your fancy. Does this really work for analog design? I am sure as tools and algorithms become more sophisticated, at some point in time the design engineer may be able to reliably design circuits by pushing the proverbial button (or simulation optimizer in this case). But until that time in the future, there is danger in relying on computers to do the thinking. As the old saying goes, garbage in equals garbage out. This is why we need to return to the idea of the napkin sessions.
Napkin sessions allowed for engineers to design analog blocks on paper and explore tradeoffs on paper using rudimentary hand calculations. As further emphasis of this need, I quote in an article from Yannis Tsividis1 , “some people lacking design experience do not appreciate how valuable this is.” This use of hand calculations quickly allowed engineers to understand tradeoffs in the design space. In addition, by understanding the sensitivities and functions of the blocks from a mathematical perspective, the designer can avoid designing and optimizing in a sub optimal design space — often an evil that plagues designers from many companies. See Figure 1.
Figure 1: A typical napkin session records brain-storming ideas during an informal meeting atmosphere.
I know that there is the tendency and pressure to finish a design quickly. This often leads to the evil of simulating without knowing what design space is best. If this starts to happen, push back and resist the tendency. It is OK to ask for more time to implement a quality design in lieu of a quick design. The quick design may cost more in the long run because your design is sensitive to process corners that often lead to more area and power. Remember, once the area is allocated for analog blocks inside a system on a chip, reducing the analog area later after a production mask is developed, does not often translate to a reduction of area for SOC without significant layout work — you're stuck, so do it right the first time.
So, if you think about carrying out a napkin session, the first question that may come up is whether or not the first order fundamental hand calculations are adequate? For smaller geometry technologies, I would argue that a first order equation may be inadequate. So what do you do? To answer this question, we need to have a tool that allows for back of the envelope type calculations. This is a possibility.
The tools needed for back of the envelope calculations to enable napkin sessions is available at some companies but should be made available at all companies designing analog blocks. The idea would be to have simple circuit blocks that run off actual simulation models that allow for information that can be used in the fundamental first order equations used for back of the envelope calculations such as unity gain bandwidth, mismatch, rout, etc. A tool that allows for such calculations may include basic building blocks such as differential pairs, current mirrors, and voltage driven devices as shown in Figure 2. For further information, please reference the following paper written in 2006 “A Web Tool for Interactive Exploration of Analog Design Tradeoffs.”2
The use of a tool such as the web-based tool referenced allows the designer to quickly understand tradeoffs for various performance parameters such as amplifier bandwidth, offset voltage, noise, output swing, etc. To gain a better understanding of this idea, I would like to explore the calculation of the input offset voltage of a simple amplifier. Please note, that although I am referring to the calculation of the input offset, I could have easily also calculated the input referred noise as both measured values are dominated by the input stage gain — please reference “A Web Tool for Interactive Exploration of Analog Design Tradeoffs” for more detail on the input referred noise.
As previously stated, the input offset voltage of an amplifier is usually dominated by the gain and offset voltage of the differential pair and the load of the differential pair. Shown in Figure 3 is a simple configuration of the first stage of a generic amplifier that could be programmed into a tool for exploring the input offset voltage of the amplifier for various device sizes and currents.
To calculate the device parameters that contribute to the total input offset voltage can be tedious and often incorrect. This is especially true when the closed form expressions in the sub micron geometries for threshold voltage, mobility, L and W do not match traditional long-channel device characteristics. Thus, there is the need to allow for calculation of these parameters to enable hand calculations of the desired performance parameters such as input offset voltage in the example. The calculations for a performance parameter such as input offset voltage involves the calculation of the offset currents of the load devices as well as the offset voltage of the differential pair.
The calculations require the derivation of the mismatch load current and offset voltage of the differential pair that are functions of the various process transistor parameters. As referenced in “Understanding MOSFET Mismatch for Analog Design” the variations of device parameters such a current mismatch or offset voltage is composed of a propagation of variances where the total variations for a parameter such as current mismatch are composed of variances of several process parameters including ΔW, ΔL, ΔVfb, Δtox , Δµ, ΔL, ΔNsub , etc. The sum of these various process dependent variations provide the information desired to assess the statistical properties of any electrical parameter that for the example mentioned is either the variance of IL or Vos.
As was shown in the reference, the variance of any electrical parameter “e” and a process parameter “i” is given by:
These process variations are used to provide the design parameters needed for the hand calculations. Because the derivation involves the calculations of partial derivatives due to local variations, the time involved is extensive and often the results could be inaccurate and cause errors in the hand calculations. Therefore, these types of calculations are perfect for using a tool that runs simple simulations based on the technology to come up with the various process dependent design parameters.
The outputs from a tool such as previously referenced, provides information on the variation of the current IL as well as the variation in Vos. These provided parameters enable the designer to easily combine the results to provide a composite offset voltage given by equation #1. Note that this example demonstrates some of the complexities of calculating the parameters needed for use in the hand calculations. In addition, performance parameters such as transconductance, rout, Fτ ,and vdsat provided from simple sims of the technology, enable the designer to calculate performance objectives such as:
By using the technology specific models, the designer can obtain accurate device parameters such as transconductance and output conductance to enable the hand calculations of these types of performance parameters. The beauty is that the designer can obtain trends of the design from these simple calculations and optimize over various performance parameters simultaneously.
The errors associated with using a simple calculation such as the input offset voltage are often insignificant once accurate values for the technology specific process parameters are available to the designer. The point is that understanding the trends from these simple hand calculated performance parameters, the designer can potentially avoid the pitfalls of designing in a suboptimal design space that may cost extra power, area, time, and future headaches.
The methodology of designing by utilizing tools to extract the process dependent device parameters enables the ability in newer sub-micron technologies and older technologies to extract simple numerical values used for back of the envelope calculations. This method facilitates an environment for the designer to engage early in the design process by using the idea of a “pencil and paper.”
Furthermore, the use of hand calculations enables the engineer to understand how the circuit being designed really works and the sensitivities that lie therein. Until the algorithms for optimization becomes reliable, the design engineer must be able to spend some time upfront understanding the circuit being designed before the plethora of simulations start. The cost for not using the idea of a napkin session can be costly to the company in lost profits, time, and possibly future opportunities.
Let me know what you think. Do you agree with these statements? Have you seen loss of time and revenue from circuits that were designed using the George Jetson method of design?
- IEEE Solid-State Circuits Magazine, Winter 2014, Vol.6 No.1, Page 38
- “A Web Tool for Interactive Exploration of Analog Design Tradeoffs,” Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
- “Understanding MOSFET Mismatch for Analog Design,” IEEE Journal Of Solid-State Circuits, vol. 38, no. 3, March 2003