A press release crossed my desk this morning that at first blush held a certain shock value. After a closer read, I found it created more questions — and getting the answers was difficult.
The press release was from STMicro and was about a topic that we discussed briefly on Integration Nation this month, process brokerage houses. STMicroelectronics and Circuits Multi Projets (CMP) announced that STMicro's “H9A CMOS process (at 130nm lithography node), which offers a large panel of analog and digital devices, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP.”
My first reaction (and the shock aspect) was that a 130nm process was being announced. Then I thought, “Oh, well, it's just for universities, and they can't afford a lot.” However, I was finally intrigued by the statement about development of “More than Moore applications,” which implies that there is something very special about this process.
The rest of the press release jabbers on about how many projects have used this service at other process nodes (including CMOS processes down to 28nm), completely eliminating the idea that this is old stuff. Still, 130nm for analog? What is the secret about this process?
The only other clue in the press release is this sentence toward the end: “ST will propose ULP/ULQC devices (Ultra Low Power, Ultra Low Quiescent Current) in the next Design Kit (DK) generations as this is a requirement for harvesting low-energy sources and for long-life autonomous intelligent systems.” But that is the future — not now. I did an Internet search and found that many, many sites had just used this press release verbatim. It also made me realize how ineffective search (even using sites such as Google) has become for finding information. The Internet has become like the newsgroups of days gone by.
More information about H9A has been very elusive. I could find nothing about it on the STMicro site. What about the CMP site? Nothing there yet. It shows an S9A run in September, which is a high-voltage process, but that would not seem to apply to circuits tuned for energy harvesting. The only thing I could find was a chip produced by Hynix that had H9A tagged on the end of the part number. This device is a 128×8 SDRAM, and the feature number of this chip is that it only consumes 4.8⋅10-11 Joules of energy per read + write. But further investigation of that device proved to be a dead end.
Why is this so difficult? Why are processes, especially analog integration technologies, such a guarded secret? I never did find an answer to my question. Is this something that only analog people are allowed to know? Is kept a closely guarded secret from digital people like myself? I am perhaps more curious than other people, who would just place a press release and forget about it. But the questions remain: What is the process, and why is it so difficult to learn more?