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What’s So Special About This H9X Process?

A press release crossed my desk this morning that at first blush held a certain shock value. After a closer read, I found it created more questions — and getting the answers was difficult.

The press release was from STMicro and was about a topic that we discussed briefly on Integration Nation this month, process brokerage houses. STMicroelectronics and Circuits Multi Projets (CMP) announced that STMicro's “H9A CMOS process (at 130nm lithography node), which offers a large panel of analog and digital devices, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP.”

My first reaction (and the shock aspect) was that a 130nm process was being announced. Then I thought, “Oh, well, it's just for universities, and they can't afford a lot.” However, I was finally intrigued by the statement about development of “More than Moore applications,” which implies that there is something very special about this process.

The rest of the press release jabbers on about how many projects have used this service at other process nodes (including CMOS processes down to 28nm), completely eliminating the idea that this is old stuff. Still, 130nm for analog? What is the secret about this process?

The only other clue in the press release is this sentence toward the end: “ST will propose ULP/ULQC devices (Ultra Low Power, Ultra Low Quiescent Current) in the next Design Kit (DK) generations as this is a requirement for harvesting low-energy sources and for long-life autonomous intelligent systems.” But that is the future — not now. I did an Internet search and found that many, many sites had just used this press release verbatim. It also made me realize how ineffective search (even using sites such as Google) has become for finding information. The Internet has become like the newsgroups of days gone by.

More information about H9A has been very elusive. I could find nothing about it on the STMicro site. What about the CMP site? Nothing there yet. It shows an S9A run in September, which is a high-voltage process, but that would not seem to apply to circuits tuned for energy harvesting. The only thing I could find was a chip produced by Hynix that had H9A tagged on the end of the part number. This device is a 128×8 SDRAM, and the feature number of this chip is that it only consumes 4.8⋅10-11 Joules of energy per read + write. But further investigation of that device proved to be a dead end.

Why is this so difficult? Why are processes, especially analog integration technologies, such a guarded secret? I never did find an answer to my question. Is this something that only analog people are allowed to know? Is kept a closely guarded secret from digital people like myself? I am perhaps more curious than other people, who would just place a press release and forget about it. But the questions remain: What is the process, and why is it so difficult to learn more?

19 comments on “What’s So Special About This H9X Process?

  1. Comfortable
    March 20, 2013

    @ Brian

    When the technology node drops to 130nm, that is the corner where gate leakage comes into play.  In other words, if you have a sample-hold with a capacitor, don't expect the droop to be near zero at voltages above a few hundred millivolts.

    At 180nm-250nm, this is pretty much a non issue.  By the time you get to 65nm a MOSFET gate looks more like a bipolar base (i.e. real current).  And huge tricks to play to get any gain out of the devices.

    Traditionally analog has always been Big-A, little-d.  So why pay the higher price for advanced digital technology if you only have 10,000 gates?  I think the gate density at 130nm is like 100,000 gates/mm.  And a mm cost a few pennies.

     

  2. BrianBailey
    March 20, 2013

    Thanks for the clarification, but that says why 130nm is good for analog, but my point was that 130nm has been available for analog for many years. What is it about this process that makes it special. I am assuming that there is something that is specifically addressing ultra-low power designs, but I don't know what it is. I am also puzzled by why it is almost impossible to find out more information about it without having to sign away my first born.

  3. amrutah
    March 20, 2013

    Brian,

      I agree that it is very difficult to access the Process Data, and would like to know if some one can throw some light about this.  After searching I found that the cost of the H9A CMOS process has been fixed to 2200 Euro/mm².  Does this say something??  Is it a promotional offer for the universities or is it that the STM is trying to characterise their process before making it available for commercial purposes…?

      

  4. Comfortable
    March 20, 2013

    @Brian

    On the CMP site they have a fairly detailed listing of the process.  Here it is below:

    Gate lenght : 130nm (drawn), 130nm (effective)
    Triple Well
    Power supply : 1. 2V for Digital, 4.6V for Analog application
    Multiple Vt transistor offering (Low Power, Analog)
    Threshold voltages (for 2 families above) : VTN = 700/697mV, VTP = 590/626mV
    Isat (for 2 families above) : TN : 280/658uA/um; TP : 104/333uA/um
    4 metal layers in standard
    Fluorinated SiO2 Inter Metal dielectrics
    Bipolar Transistors NPN
    Typical beta : 90
    Ft Max @ Vbc=0 : 2,4GHz
    2 specific implant levels : NDRIFT & PDRIFT 
    MIM 5fF/µm2  capacitor
    Double gate oxide for analog features

    Having worked in analog for a while, I can tell you the pieces above that are “special”.

    NPN with beta = 90

    Triple Well, NDRift and Pdrift which enables higher voltages and fully isolated N and P devices.  Fully isolated with wells is important to keep switching noise out of analog circuits.  Otherwise all the noise is on a common backplane, the substrate.

    MIM capacitor at 5fF/um2

    XFAB is a main player in mixed-mode technology also.  They only support down to 180nm and do a bangup business at that node for the reasons I posted in my earlier email.

    Hope this is more to the point of your question.

     

     

  5. BrianBailey
    March 20, 2013

    Thanks Comfortable. When I first wrote the article I did look on the CMP site but they had not yet got any details up about it. I will ponder the figures and see if there are other interesting stories hidden amongnst the numbers.

     

  6. Brad Albing
    March 21, 2013

    Has to do with thickness of oxides, breakdown voltage, and acceptable margin/tolerances with respect to the breakdown voltage. So we'll just have to cope w/ 4.6V span instead of 5V.

  7. Netcrawl
    March 23, 2013

    Thanks for bringing us this great article, yes I agree with @Scott what's with the numbers? What was wrong with 5V+/- 10%  and what exactly this one bring in the table?

  8. patrick_m
    March 25, 2013

    Hey Brad, voltage rails continue to drop, though, especially as we integrate more: What are the implications of that?

  9. Brad Albing
    March 25, 2013

    I can turn that around – with smaller geometry processes, voltages need to be lower (lower breakdown voltages for the thinner layers). Also, for faster parts, a lower voltage span means it's easier to swing from rail to rail in less time. So even the digital guys need to be aware of slew rate: much easier to slew from 0.0V to 1.0V in 1 nanosecond than it is to slew from 0.0V to 5.0V

  10. Jack Shandle
    March 26, 2013

    As someone who has read, been puzzled over and rewritten many news releases over the past 20 years, I might be able to shed some light on the H9X new release's opacity.

    1. The person who wrote the release did not understand the subject matter but had a tight deadline to finish it.

    2. The target reader may have been financial analysts, not engineers. (Did STM's stock move much after the announcement? Answer: not much. It's been hovering around $8/sh through March but down from $9/sh (-10%) in February. STM will probably report quarterly results March 31.

    Marketing studies have shown that the number of news releases a company produces over time has a measureable effect on stock price (price tracks number of news releases). This used to be attributed to day traders who don't understand technology but are willing to place a bet anyway, reasoning that the company would not issue the news release unless the news as significant — Wrong. According to MarketWatch, more analysts are recommending a BUY than 3 months ago. (I am not suggesting this is due solely to news release volume, btw.)

    3. The STM plant in Rousset is looking at excess capacity after September 2013, which is why that month is named to carry the first prototypes, or, come other financial aspect of that particular process.

     

  11. BrianBailey
    March 26, 2013

    In some respects, the voltage reductions are not happening fast enough. The amount of decrease with each node is leveling out and since power is related to the square of the voltage, this is one of the reasions why power is becoming such a big problem. So, voltage reduction is “generally” good for digital, but not so good for analog because that means the linear regio is getting smaller and noise becomes a bigger problem.

  12. amrutah
    March 26, 2013

    @Brian:  “the voltage reductions are not happening fast enough”, I agree.  Though the voltage scalling is done with every process node, but the voltage reduction below 1.1 or 1 V is not going fast. This could probably because of the VT of the transistor not getting reduced appreciably.  If we look at 350nm process and 45nm process the VT hardly varies from 800mV to 650mV (that considering worst-case).

  13. Brad Albing
    March 26, 2013

    I think we should go back to +/-15V supplies for analog.

  14. BrianBailey
    March 27, 2013

    And why not stop all of the serial nonsense and go back to nice fat cables for everything! Valves always were better!

     

  15. Brad Albing
    March 27, 2013

    Exactly so. I still like the 12AX7 for my pre-amps. By extension, we can go back to the 12AU7 or the 6SL7 for the flip-flops in our computers.

  16. Brad Albing
    March 27, 2013

    Or even 0 to 10V in the days of digital design w/ those new-fangled CMOS 4000 series devices.

  17. BrianBailey
    March 27, 2013

    I can still remember most of the components in the TTL handbook! I so loved 5V. Anyone know what geometry the original TTL parts were in?

  18. Brad Albing
    March 27, 2013

    Not me; someone here will know, I'm sure.

  19. Nando Basile
    June 5, 2013

    Brian and All,

    I apologize for late reply, just dropping on the blog now. Anyone still reading?

    There is nothing special in H9A technology apart that is a very good platform to start doing analog research for ULP/ULQC, both from technical and cost effectiveness standpoint.

    What ST wants to do here is sharing this platform with labs and research center as a first step of a wider, common research project, aiming to get their feedback about its future evolution to serve the market of autonomous objects.

    I think Comfortable was proposing a pretty close interpretation of it.

    The key point is not the techno as it is today, but as it will evolve tomorrow. ST has plenty of ideas of evolutive and disruptive approaches (as other Companies do) that are going to be implemented in the technology platform and shared. That will hopefully allow research partners to reach new performances in the ULP/ULQC realm and ST to leverage on the feedback of clever analog designers for technology solutions better supporting their future application. The research landscape in Europe is much more fragmented and complex than in U.S. Diversity is more difficult to manage, but diversity opens the way to more ideas. H9A is as well a bet on as a sort of ''living forum'' for such designers to test their solutions.

    For any more information, feel free to ask me directly.

    Best Regards,

    Nando Basile ()

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