In my last posting When Developing New Silicon IP, Is First Pass Success Possible? Part 1 , I covered several questions for reaching first pass success. In this series, to reach first pass success there are some questions you can ask yourself as a team and get answers to before you move too far along the design path and need to make painful adjustments later down the road that cost money, area, and time. Having said this what else could you review as a design lead with your team or a manger developing a new product.
Is this a general market part or fully custom?
This question is important because the requirements from a fully custom IC can be vastly different than a general market IC. When the part is being developed for the general market the design and system teams must comprehend possible use cases and plan accordingly. For a general market part the relation with the customer may not be available so without a proper search and probing the various customers the part will service, the designed IC may miss targets or not meet the functionality requested.
Has the technology you are developing the IC on reached full M3 maturity?
If the process has not reached maturity, the models could change and or the extracted parameters used in the models may change or are not correct. So risk is present for complex analog circuits. Such as flicker noise. As the process matures the flicker noise parameters can significantly vary from maturity level M1 to M3. So, if your models are based on a M1 or even M2 maturity, then the flicker noise could and probably will be different. Therefore, designers need to be aware of weaknesses in the design and where a possible model change will have vastly negative results on the final silicon. So, the designer must plan for workarounds as much of the time, designers are forced to design on technologies that are not fully matured. This is due to the points made earlier about the need for faster turn time on innovation driven from customers.
Have you communicated appropriate risk to the customer to negotiate specific spec relaxations for the more difficult parameters in an effort to provide margin?
It is important for the customer to clearly understand the risk with aspects of the design being developed. For tougher specifications, it is prudent for the design lead and or system lead to interface with the customer to understand where spec relaxations are possible and where specification must be met. The first initial response will be to say all specifications are important and must be met. This is understood but as with any complicated IC development some specifications will be marginal and depending on the confidence in your models and system design, targets may be missed. Therefore, it is important to understand from the customer which are the most important specifications and target your design resources to thoroughly come up with just in case scenarios and workarounds to meet the specifications that are deemed most critical. I would recommend prioritizing the specifications with the customer in levels of importance before the actual IC development begins.
Does the design team have access to correlation data of the simulations models used for development against silicon data?
To follow best design practices, if possible understand where the simulations models match closely with the silicon extracted device parameters and where there are weaknesses in the quality or confidence of the extracted parameters used to create the silicon models for simulation. By understanding where the models match and where they are off, the designer can adjust his or her design to include extra margin. This understanding would include the idea of knowing where the models fit the data and in what region of operation this is true – and likewise understand regions of operation where the models clearly are deficient. Furthermore, it is important to understand if the process characterization devices sizes match up to the choices used in the design; if not additional error will exist. This understanding is important to know where your simulations models are weak and where it is necessary to add margin in the design because correlation data does not exist or it is not possible for the models to accurately predict a behavior (especially true for complex high performing analog functions)?
In addition, if the technology is new and not at full maturity, it is important to take the appropriate margin in your designs and communicate the risk. Likewise, if the technology has not reached full maturity as previously stated, it may be prudent to negotiate for reduced sets of specifications for limited use cases (i.e., reduced temperature range over which the full specification is met).
Have you included additional control bits to provide what if scenarios to allow for variations in the circuits not planned? Provide options to change bias currents, voltages, etc.
The inclusion of additional just in case control bits is very important for new IP. As new analog IP is developed, there are cases as previously discussed where the simulation models available to the design team have known deficiencies or questionable correlation to silicon. In addition, you may be unsure that your own circuit designs do not have the margin needed. This can often be the case for blocks as part of the lineup of an analog front end or some other block as part of a larger embedded system. In these cases and others as well, planning for uncertainty can make the difference between a first pass success and the need for more spins of silicon. What this means is that you develop the control ability to increase or decrease critical bias currents (i.e., to give an amplifier more bandwidth by increasing its bias currents). Furthermore, you may need to change common mode voltages or supply voltages for compliance concerns. Maybe you need to trim in specific RC parameters of a feedback system, etc. Now, before you get the impression I am suggesting going hog wild on the use of control bits know that I am not. The use of additional control bits is not free and takes additional routing and control logic that means more area and potentially degraded performance of the control circuits connect to parasitic sensitive nodes. However, I am saying that the design lead should sit down with the designers and discuss the critical parts of the circuit that are sensitive and need additional margin in the form of bias currents, etc.
In conclusion, in this two part series, I have outlined 10 separate statements or questions to ask yourself when trying to define your own level of risk and how you can possibly mitigate some of the risk to make your designs a first pass success. These 10 sections are not meant to be exhaustive but do provide some background questions and concerns that must be considered. Hopefully, by following and using some of the ideas presented you can find yourself in the winner’s circle with a first pass success in your corner.