When Grounds are Separated

Question: Where do I connect the grounds of switching regulators?

Answer: How should you proceed with a switching regulator with an analog ground (AGND) and a power ground (PGND)? This is a question asked by many developers designing a switching power supply. Some developers are accustomed to dealing with a digital GND and an analog GND; however, their experience frequently fails them when it comes to the power GND. Designers then often copy the board layout for a selected switching regulator and stop thinking about the problem.

PGND is the ground connection over which higher pulsed currents flow. Depending on the switching regulator topology, this means the currents through a power transistor or the pulsed currents of a power driver stage. This is especially relevant in the case of switching controllers, for example, with external power switches.

AGND, sometimes called SGND (signal ground), is the ground connection that the other, usually very calm, signals use as a reference. This includes the internal voltage reference needed for the regulation of the output voltage. Soft start and enable voltages are also referenced to the AGND connection.

There are two different technical philosophies, and thus different opinions among experts regarding the handling of these two ground connections.

According to one philosophy, the AGND and PGND connections on a switching regulator IC should be joined to each other right next to the respective pins. This keeps the voltage offset between the two pins relatively low. Thus, the switching regulator IC can be protected from disturbances and even destruction. All of the circuit’s ground connections and a possible ground plane would be linked to this common point in a star topology. Figure 1 shows an example implementing this philosophy. The board layout for an LTM4600 is shown here. It is a 10 A step-down micromodule. The separate ground connections on the board are joined right next to each other (see the blue oval in Figure 1). Due to the parasitic inductance of the respective bonding wires between silicon and the housing, as well as the inductances of the respective pins, there is already a certain amount of decoupling of PGND and AGND, resulting in a low amount of mutual interference between the circuits on the silicon.

Figure 1

Local connection of PGND and AGND right at the solder contacts.

Local connection of PGND and AGND right at the solder contacts.

The other philosophy involves additional separation of AGND and PGND on the board into two separate ground planes connected to each other at one point. Through this connection, interfering signals (voltage offset) remain largely in the PGND region, while the voltage in the AGND region remains very calm and decoupled very well from PGND. However, the disadvantage is that, depending on the transients in the pulsed currents and the current intensities, there may be a significant voltage offset between PGND and AGND at the respective pins. This can lead to improper functioning of, or even damage to, a switching regulator IC. Figure 2 shows an implementation of this philosophy. This comes from an ADP2386, a 6 A step-down switching regulator.

Figure 2

Separated AGND and PGND connected under the GND tab by vias.

Separated AGND and PGND connected under the GND tab by vias.

The grounding question comes down to a trade-off between strong separation with the advantage of separating noise and disturbances and running the risk of generating voltage offsets between the two grounds, and thus causing harm to Silicon and compromising functionality. The right decision to make in regard to this trade-off is heavily based on the IC design, including switching transition speeds, power levels, parasitic inductances on bonding wires and IC package, and the latch-up risk of each IC design involving the individual semiconductor process.


The answer to the question of how to deal with the grounds AGND and PGND is not that simple. That’s why this discussion continues. At the beginning, I mentioned that many users of switching regulators adopt the board layout and the ground connection type from the example circuit supplied by the IC manufacturer. This procedure is useful because you can usually assume that the manufacturer also tested the respective IC in this configuration. It can also be seen in the examples given in Figure 1 and Figure 2 that the respective IC pinout is suitable for local ground connection close to PGND and AGND, or for separate grounding.

Of course, an IC manufacturer may make mistakes when designing example circuits. That’s why it’s good to have some further information about the underlying philosophies.

About the author

Frederik Dostal [] studied microelectronics at the University of Erlangen-Nuremberg, Germany. Starting work in the power management business in 2001, he has been active in various applications positions, including four years in Phoenix, Arizona, working on switch-mode power supplies. He joined Analog Devices in 2009 and works as a power management technical expert for Europe.

3 comments on “When Grounds are Separated

  1. alicetaylor
    November 22, 2018

    Your topic is very great and useful for us…thank you


  2. raleighsimon
    November 28, 2018

    nice post

  3. EE-Bob
    November 28, 2018

    When selecting a switching regulator IC, in addition to availability, cost, part count, performance, and believability of modeling/simulation tools, I also consider if the circuit can be laid out on a single layer … and more inportantly, with a single, contiguous ground plane (PGND) where the input/output capacitors, IC and feedback/loop conpantens can connect. The plane can be poured over an internal GND layer, but the vias used to connect the local PGND plane to the internal GND plane need to be carefully considered. A single via is great, but output currents may require more. These should be grouped as tightly as feasible. If the IC uses a thermal-pad, the vias can be placed under this pad to help with thermal performance. (However, consult your PCB Assembly CM for DFM concerns!) Location of these vias will also drive undamped/snubbed inductance in the switching node that can lead to ringing affecting you EMC performance.

    This approach most resembles that of Example #1, only in a vertical stack rather than co-planar.

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