Moore's Law has been driving digital integration for a few decades, and it provides a circular reinforcement. Being able to create smaller devices means that more can be placed on a die. This provides added functionality, decreases costs per device, and makes demand for the end product larger. This spurs another round of integration and geometry reduction.
Up until the 90nm node, almost every aspect of this cycle fed into the next one — reduced voltages, faster devices, reduced power. But then things changed. Leakage became significant. Wire delays became larger than gate switching times, and wires became more variable in length, so design was no longer independent from backend considerations such as place and route. But the drive for integration continued, and that meant bringing more analog material on to the chip. However, what is good for the goose is not necessarily good for the gander, and geometries such as 28nm are not particularly analog friendly.
Aggressive voltage reduction has been important for controlling power consumption in the digital circuitry. Most 28nm chips now operate at less than 1V and have IO voltages of 1.5V or 1.8V. This creates noise and offset-voltage constraints.
Other problems come from the complexity of the design rules for newer geometries. Multiple transistor sizes used to be available, but it is now common for gate area and transistor width and length to be limited to a certain set of combinations.
Many have argued that the analog portions that are integrated on to the chip will have to continue using older technologies, but this would mean that the analog block would consume a higher percentage of the total chip and thus add significantly to the total costs. Some have suggested that eventually this would lead to analog being pushed off the chip again. I don't buy into that theory. It assumes that nothing can change in the analog world, and that is far from the truth.
This and many other factors may make the situation look tough, but when this happens, it is time to look for some alternative solutions. That often means adopting new architectures, such as digital calibration or control to help the integration of the analog circuitry and help it adapt to random variations. This creates some interesting challenges, because the two groups and two sets of tools are being forced together closer than they were in the past. We can no longer talk about big this and little that — each is just as significant as the other. More importantly, it is not possible to separate them as has been done in the past. I will discuss these issues in detail in a future blog.
Another possibility is a change from voltage mode circuits to current mode circuits. The argument is that voltage swings are slowing because of the increasing device and wire capacitances. But these do not affect current in the same way. The threshold voltage of transistors is the key factor that is constrained by the noise floor level. But circuits can operate in the sub-threshold region. This is also a subject for a future blog.
How do you handle analog circuitry in a small-geometry digital fabrication technology?