Advertisement

Blog

Where Are Your Analog Design Models Accurate?

Oftentimes the models that come from the manufacturing site are accurate for specific design use cases but may not be accurate for the types of designs targeted by your company or, more specifically, the design group. Why is this so? Is this actually correct? The problem with producing models is that it is difficult to characterize the various sizes and lengths of transistors available for potential use in embedded circuit designs.

Creating the various structures needed for each transistor type at various lengths and widths is not only prohibitive, especially when monitoring these structures as part of a process control monitor module, but creating the combination of the various available sizes is also prohibitive from a characterization perspective. As shown in Figure 1, models cannot be fit in every region of operation. Therefore, inaccuracies not only exist because the specific transistor size and transistor current density is not characterized, but also because it is not reasonable to characterize all regions of operation for the transistor.

Figure 1

Limited data points taken to characterize model.

Limited data points taken to characterize model.

Because models cannot be fit over all regions, it is important to obtain feedback from design as the technology is being developed to choose devices and current densities that are best fit for the design use case. The choice of specific device sizes and structures should be placed as part of the characterization structures for the technology. Given the difficulty in characterizing all of the various device areas that would be appropriate for design, another option that should be explored is to place working circuits on the characterization mask set and, if the circuits are simple enough, even considering placing these circuits in the process control monitor.

The choice of these circuits could allow feedback on how the models represent the silicon in more general terms and can be used to verify several design parameters from offset and bandwidth to noise. These are important and pressing issues that face designers that want to obtain the Holy Grail of first-pass success, but it is only fair to mention that model accuracy has improved significantly with the development of the Surface Potential model and improvements to the BSIM4 model, which suffers from a discontinuity at zero Vds — another discussion to have later. With this being said, what are some of the types of parameters that should be captured for analog design?

Shown in Figure 2 is a plot of some important parameters to capture when looking at model development. The idea is to choose devices and current densities that are biased appropriately for typical analog design regions of operation. For instance, make sure the device is based in strong inversion and biased with Vds on the order of 300 mV. The use of devices with analog regions of operation in conjunction with creating circuits that provide feedback on several design parameters is no guarantee that your modeling will be correct for a particular analog design. However, the idea of engaging the appropriate senior design experts during the development of the technology will improve the probability of first-pass success on circuits that use the models developed.

Figure 2

What is needed in analog models.

What is needed in analog models.

To reiterate, I believe it is important for designers of the analog blocks to be involved in the development of the process by providing feedback on what is needed in the technology and provide feedback to the process engineers on the most important parameters to track. In addition, because it is not possible to hit all transistor parameter targets, the design community must prioritize on those parameters that are most important and relevant to analog design. Furthermore, as part of the need to have feedback and involvement from the design community experts, equally important is the idea of producing what is called a “loop closure report.”

This report provides information on how well the silicon devices fit to the model simulations. The loop closure report should include active and passive devices and report performance on the various important design parameters given to the process engineers by the design community. The compilation of such a report is extremely important during the beginning phases of maturity. I am sure it is safe to say that many designers across various companies are sometimes pushed to design on process technologies that have not yet reached maturity. Because of this need to start design on newer technologies to keep up with the competition, the involvement by the design community becomes even more important, and producing such reports helps the designer provide that needed feedback.

I would like to say that as companies move to foundries to use vanilla process technologies, the interaction with design and process technology becomes more difficult during the development process. However, the design community can involve the companies' own process engineers in developing characterization structures and interact with process engineering experts to feedback comments from the design community to the foundry where the technology is being developed.

Do you feel confident in your analog models? Do you interact with process engineering to drive characterization and PCM structures? What have you found effective when ensuring the models you design will meet the analog performance parametrics?

6 comments on “Where Are Your Analog Design Models Accurate?

  1. RedDerek
    June 26, 2014

    I take modeling very seriously – not. I will simulate, but I scrutinize the results for general understanding. My real test is always circuit testing. As Bob Pease commented – do not always trust simulation, it can lie.

  2. amrutah
    June 30, 2014

    @RedDerek:  “…do not always trust simulation, it can lie”.

       I agree with what you are saying.  There can also be another culprit in the form of simulator that we use.  It uses the models and then depending on its convergence and other algorithms can give deceivingly correct results.

  3. amrutah
    June 30, 2014

    @Brandth,  I agree that the information the Fab guys release are for some specific device lenghts and widths.  But the models coverage is for atleast 10 different W,L combinations and before the simulation the models can be binned together and a nearest values be choosen.  I understand there is some sort of curve fitting that goes in here but then we do have the USL and LSL defined that cover the missing gaps.  Don't do they??

  4. amrutah
    June 30, 2014

    @Brandt,  “To reiterate, I believe it is important for designers of the analog blocks to be involved in the development of the process”

      I agree that the designer has to be involved in the process development but I think it is both the digital and the analog designer. With the shrinking of the process nodes and high speed circuits/systems the timing becomes critical.  If the digital logic is being built using a library of cells then we can force the digital designer to build circuits using specific Fab characterised W/L's but if the digital logic is to be custom built (from power and leakage reduction point of view) then involving the  digital designers will help develop the process node.

  5. Sachin
    June 30, 2014

    do not always trust simulation, it can lie.

    @RedDerek, totally agree with you on this. Its not right to trust simulation results because sometimes the model files being used have limitations. Its always better to cross check the simulation results using hand calculated results.

  6. Sachin
    June 30, 2014

    if the digital logic is to be custom built (from power and leakage reduction point of view) then involving the digital designers will help develop the process node.

    @amrutah, I totally agree with you. I think its better to build custom digital library if the number of digital cells used in the design is limited. Moreover it takes lot of effort to build digital cells and characterize them for optimal performance.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.