High-performance data acquisition signal chains used in industrial, instrumentation, and medical equipment require high dynamic range and accurate signal measurements while simultaneously addressing tough space constraints, thermal, and power design challenges. One of the ways to achieve a higher dynamic range is to oversample the converter to accurately monitor and measure both small and large input signals from the sensors.
Oversampling is a cost-effective process of sampling the input signal at a much higher rate than the Nyquist frequency to increase the signal-to-noise ratio (SNR) and resolution or effective number of bits (ENOB). As a general guideline, oversampling the ADC by a factor of four provides one additional bit of resolution, or a 6dB increase in dynamic range (DR). The DR improvement due to oversampling is defined by:
   ΔDR = log2 (OSR) × 3dB
In many cases, oversampling is inherently implemented well in delta-sigma (Δ-Σ) ADCs with integrated digital filtering functionality, where the modulator clock rate is typically 32 to 256 times higher than the signal bandwidth. But oversampling is tougher to implement when fast switching between input channels is required.
SAR (successive approximation register) ADCs are also popular for the channel multiplexed based architecture that requires fast response to step input near full-scale (worst case) amplitude without any settling time issues. However, this puts an extra burden on the driver amplifier's requirements. To settle a kick-back coming from the switched capacitor DAC array of the SAR's input, an amplifier must have very good performance in terms of bandwidth, slew rate, and output drive capability. If it does not, non-linear effects will manifest in the output response.
The high throughput rate of a SAR ADC does allow oversampling. In this case, the low noise floor (achieved via a combination of low RMS noise and high throughput) with linearity is critical. Some of the high-performance SAR ADCs provide increased bandwidth, high accuracy, and discrete sampling in a small time window required for fast control and measurement applications. The fast throughput rate and low power with a small package size helps designers to meet space, thermal, power, and other key design challenges common to high-channel-density systems.
Although both ADC topologies can accurately measure signals extending down to DC, the SAR architecture usually allows the ADC core power to scale with the throughput rate. This minimizes the power consumption by at least 50 percent, which helps to meet the thermal constraints. In comparison, the Δ-Σ ADC typically has a fixed power draw. An example of high throughput together with power scaling can be found in ADI's 5MSPS 18-Bit AD7960 SAR ADC.
Oversampling with a SAR ADC can improve anti-aliasing and reduce noise. The low-pass filter that is placed in front of an ADC is there to minimize aliasing; but it also reduces noise by limiting bandwidth. The high oversampling ratio plus digital filter profile of the Δ-Σ ADCs minimize the anti-aliasing requirements at their analog inputs. Oversampling in the ADCs modulator reduces the overall noise.
SAR architecture without latency or pipeline delay enable fast control loops design. The SAR ADC such as AD7960 offers the lowest noise floor relative to the full-scale input floor, resulting in a higher SNR and excellent linearity performance. Even so, it cannot reject the 1/f noise close to DC (50/60Hz) content unlike Δ-Σ ADCs. There are a number of other ways to increase the dynamic range of an ADC such as adding ADCs in parallel and interleaving them in time. However, some designers may find this method to be cumbersome or impractical to implement for their system mainly due to the power, space, and cost reasons.
Have you designed with SAR and Δ-Σ ADCs? What problems did you have with them and how did you work around those problems?
Related posts:
- ADC Noise: Where Does It Come From?
- Interleaving Spurs: The Mathmatics of Timing Mismatch
- ADC Basics, Part 9: PGA Embedded in an 8-Channel, 12-Bit SAR
- Signal Chain Basics #80: Optimizing Power vs. Performance for a SAR-ADC Drive Amplifier
- ADC Guide, Part 13: Input Impedance
- Data Converters in Massively Parallel Analog Systems
- ADC Basics, Part 4: Using Delta-Sigma ADCs in Your Design
- ADC Basics, Part 3: Using Successive-Approximation Register ADC in Designs
- ADC Basics, Part 2: SAR & Delta-Sigma ADC Signal Path
@Maithil nice blog! thanks for sharing this one. Actually its a good match, picking the right suff is not esay, first things to do is to take some key factors in choosing the right one like conversion accuracy, who get the most scores in this area, accuracy is a component of gain erros and this is very important. Then there's the conversion speed, linearity strikes, differential linearity and last the quantization error. Its a process, but overall we can still get the better.Â
Maithil,
Nice post.
SARs provide us high thoroughput. Sigma Delta ADCs such as cirrus CS5460, ADS1298R, etc. provide nice 24 bit conversion. For scaling up a SAR ADC's ovesampling would help as you mentioned. For a pressure sensing application, we used a 10 bit adc and could achieve a 12 bit conversion through oversampling. It worked fairly well.
I guess often noted or observed problem with SAR is presence of large variance in the o/p code for a dc i/p.
Samicksha,
This could be corrected by moving average. You can stabilize the counts. However, upto 10 bit ADC resolution, you may not have so much of jumping. If you go beyond that, may be, you need to work on filtering.
Maithil, you have given very good insites in the ADCs. You have cleared lot of things for noice as well as basic difference between SAR and Sigma Delta ADCs. Being young engineer it is really informative post for me.
@JK, I have used input filtering as well as rolling average in the application of Static Voltage Stabilizers for the close loop. It gave pretty good results. We also used 10 bit resolution for that. This is nice technique for removing alising errors while measuring DC signals.
Both have their own strengths, SARS can have embedded multiplexers while some Delat-Sigma have multplexers, SARS target applications that require fast response and low latency while Delta-Sigma atrget applications that require high resolution like sonar etc.
@samichsha you're right, its a common issue and a huge disappoinment for using SAR, actually the problem is not on converter, its about how do we implement the application circuits.
I wonder whether there is a comparison data analysis of current consumption between SAR and Delta-Sigma ADC. Typically, in portable electronic gadgets, expanding for battery life is very critical factor, even though digital output resolution affects the system performance. It is not necessary for some application to get the high resolution which might overload CPU horsepower and price. I thought that comparison would be slightly different among semiconductor chips.
Delta-sigma-ADC expertise has held up to that of SAR ADCs in sampling frequency. A limit in sampling-time areas of almost 100 kHz to 1 MHz happens in both sorts of devices. These 2 sorts of converters also match in maximum key specifications.
Maithil,
I have a basic question about the name of the ADC. ADI in the past called them sigma-delta converters. Now I notice that they are being called delta-sigma converters. Has some standardization of the name occurred in the industry?
You are right netcrawl, SAR converter has a wide input bandwidth, but at application level how do we identify b/w these converters.
Vishal,
Moving average is a handy technique used all the time in Analog intensive applications. I remember a Analog Devices application note on weighing scales and a high resolution ADC where they have also given techniques to make the display change in proportional to incoming data while still maintaining the averaging.
I have use moving average techniques even in RPM measurements.
Dennis
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I have a basic question about the name of the ADC. ADI in the past called them sigma-delta converters. Now I notice that they are being called delta-sigma converters.
Some time ago I heard Bonnie Baker (IIRC) suggest that the word inversion happens at the Mason Dixon line.
Hello Everyone,
Thanks for sharing your thoughts and feedback on this.
Regards,
Maithil
Implementation view point:
We might consider not only resolution (bits), but also max sampling rate, differential nonlinearity, Signal noise ratio, power consumption and unit price in addition with I/O type such as SPI and serial LVDS. A different application may yield a different preference.
You are absolutely correct on the point you made.
But oversampling is tougher to implement when fast switching between input channels is required.
Agreed, oversampling is tougher to implement when fast switching happens and that is the reason sigma-delta finds application in low-frequency applications.