Jim Solomon came out of “retirement” earlier in the year to lend his support to CiraNova, an EDA startup developing an interactive layout tool for analog ICs. The former National Semiconductor design chief and founder of Cadence Design Systems told EE Times that it was a pleasure to be “doing analog” again. It was an increasingly smaller specialty for Cadence, which once devoted a whole division to analog design. “You have to stay focused,” Solomon added, an accusation reminiscent of one leveled at many broadline suppliers.
Indeed, among the EDA design tool vendors, analog appears to be getting short shrift. Cadence no longer calls its famous platform “analog artist,” and the promotion of specialized simulators and handcrafting tools has been folded into its “custom IC” group. Mentor Graphics promotes a front-to-back analog design capability, but its keeper is the company's “deep-submicron division.” (Its biggest announcement this year for “analog designers” was an interactive layout tool. “We've always had a automated tool for placement and routing,” Mentor told me. “This one's interactive .” It allows the analog experts to assert a little personal control over the automated process, without stopping it in its tracks.)
Synopsys, which bought Avanti (Epic and Anagram before that), has an equity investment in Analog Design Automation (ADA), but has yet to make a strategy statement about analog (or mixed analog-digital) IC design. ADA, in fact, authored the main feature for the Planet Analog magazine folio that appears next week (August 18). The article is about circuit optimization techniques for analog circuits, and describes how a PHY-maker was able to juggle parameters like performance, jitter, noise, and silicon area using ADA's tool. But Amit Gupta, ADA's founder and business manager told me a curious thing: While he believes the culture inside a company like Synopsys is very analog savvy, there is an increasing use of the term “deep-transistor design.”
That analog intellectual property (IP) is in demand, there can be little doubt. The evening panel on Analog IP I attended at this years International Solid State Circuits Conference (ISSCC) was frankly much more optimistic about the business prospects than a similar panel I chaired at the Design Automation Conference (DAC) the summer before. Everyone still agreed the Virtual Socket Initiative Association's (VSIA) spec writers would go blind trying to generate the hernia-making documentation that defines all the conditions for analog intellectual property trade. They still agreed that analog IP requires a tremendous amount of implementation hand-holding as it moves from provider to user – just to get the devices working properly – a fact which makes analog IP trade closer to a design services business that a fabless semiconductor trade.
But optimism prevailed, if not for the quality of the EDA tools, then for the design robustness of the properties to be traded. I thought, in the question-answer session, it would be easy to poke holes in the arguments presented by the panelists, primarily tool vendors and IP vendors. But I thought I'd turn the question around to the audience. “If you guys could get what you wanted from analog IP,” I posited, “How many of you would actually buy this stuff? (Raise your hands).” The responses were tentative at first; there were roughly 300 people in room. It saw a sea of hands.
If there's such a demand for analog IP, why are the analog EDA startups (and IP providers) having such a rough time? Why did analog methodology/tools/IP vendor Antrim Design Systems rollover and die (or, rather, whisper, “Cadence, take me”)? Why did BTA become Celestry become Cadence? Why is NeoLinear too within Cadence's gravitational pull? Why is the business fate of Barcelona Design such a mystery?
The answer is that the “Sea of Hands” I witnessed at ISSCC is not the same as purchase orders. We've all seen the market forecasts that suggest as many as 70 percent of all new ASICs will have some form of analog or mixed-signal content by 2006. Do you still believe that? Yes, there are elaborate fantasies circulating about the single-chip cell phone, which integrates the RF circuitry (even the power amp) with the baseband processor. It uses 100MHz direct conversion, communicates on GSM and CDMA, even extracts MPEG video streams and plays MP3 audio. This is NOT Black Magic; it is NOT a technology issue; it is dollars-and-cents. To the ISSCC crowd I say: “Supposing I can give you the IP to do this, but you have to put bipolar driver transistors (maybe SiGe) on your CMOS substrate. Let's say: Five additional mask steps. Would you still be interested?”
“I can give you the A/D converter you need, but it's a little tricky to lay out: For 10 percent of your silicon area, it'll cost you 30 percent of your wafer yield, and maybe double the price of your die. Would you still be interested?”
“Oh yes: we're going to route some tuning signals off chip to passive component networks and then send them back on chip. Your 256-lead gull-winged flat pack needs to be a 512-point BGA. Would you still be interested?” Watch the hands drop.
In this economic climate, the IP that has any chance of flying off the shelf consists of interface components. These include line drivers (or well-characterized FETs) that enable the big digital what-cha-ma-call-it to drive a big fanout load (an array of surrounding logic devices). Also, to avoid the zillion-pin packaging scenario, engineers will clock their data in serially, and this creates demand for Serdes parts (serial-to-parallel converters) and phase-locked loops (PLLs). Artisan Components, which bought analog IP vendor Nurlogic Systems earlier in the year, may have a pretty good take on this. Callen Carpenter never said “cheap-and-dirty” about the parts his company markets on the web, only that Artisan was not out to displace an Analog Devices or LTC. After you account for interface components, I suspect analog IP business drops off a cliff.
So where are those 80,000 digital design engineers Gartner Dataquest says could benefit from analog design tools? The reality is that they are there (assuming they're not unemployed). They're at Intel, and STMicro and Toshiba and all those smaller companies punching each other for shares of the IEEE802.11 chip market. They're at Delphi and Infineon. They're at AMD and Philips. They calculate IR drops across the surface of a big digital chip. They look at the effects of package lead frames and PCB line lengths on signal integrity. They run HSpice, HSim and other full-chip simulators until they're ready to puke. They model the effects of RF noise or adjacent channel interference on bit error rate (BER). They just don't call it “analog.”