Santa Clara, Calif.
A fabless semiconductor company developing audio/video compression systems-on-chip and solutions for the consumer, PC/Mac and surveillance markets
Latest project: 0.13-micron (UMC) video decoder device for high-definition TV, high-definition DVD and video adapters
Design team: 20 engineers
Design tools: Synopsys VCS and PrimeTime, Cadence Design Systems Specman and Conformal, Magma Design Automation Blast Fusion, Sequence Studio, Mentor Graphics Calibre
A few years ago, the design team at WISchip received a sample of a video encoder chip from the fab and made it operational in two hours. Then it tested the chip on a real TV screen and found that just changing the channel or hitting fast-forward on the VCR hurt video quality, said Shuhua Xiang, vice president of engineering and chief technology officer.
These days, WIS is much more careful about building safeguards against these “corner cases.”
For its first SoC decoder chip, due in the third quarter, the company took no chances. It's using software simulation, FPGA-based emulation and its own test software to make sure that the video won't crash when it encounters something out of the ordinary. “The idea is to put randomness into the video stream without violating the semantics of the video stream,” Xiang said.
When it started the project 18 months ago, the design team put a lot of emphasis on modeling the chip in C first. The idea was to create a unified design flow emanating from a high-level language so that the team members wouldn't have to use too many formats, Xiang said.
Another key move was to assign verification engineers to hammer on the design rather than have the designers cross-check their work. “One class of people doing the design, another one breaking it,” Mannos said.
In the future, the design team would like to shift to a C-to-RTL tool to handle much of the up-front design work. But, today, the tools are too protocol-based to be practical. Ideally, said Xiang, he'd like to see C-level design tools be able to handle different abstraction levels in a unified design flow. In the short term, Xiang said, he'd like to see more top-level design tools with predefined modules that link to Verilog, firmware and C.
Senior verification engineer Medel Dace would welcome a verification tool smart enough to handle the routine test cases automatically so he can concentrate on the corner cases. “Sixty percent of our time is now spent on simple test cases,” he said.
Director of engineering Chino Lin's wish list includes a back-end tool that can fix noise and power problems and perform sign-off in one shot. Today, those steps require different tools from different vendors, he noted.
'One class of people doing the design, another one breaking it.'