Xilinx develops FPGA-based deserializer for TI’s ADS6000 ADC line

San Jose, Calif. — Xilinx, Inc. has announced the availability of a Virtex-4 FPGA-based deserializer reference design, application note and evaluation module. Developed jointly with Texas Instruments, the reference design, together with the application note, deserializes data streams from TI's ADS6000 analog-to-digital converter (ADC) family.

Designers can leverage the evaluation module as a rapid prototyping environment for designing digital circuits that directly interface to the ADCs. The evaluation module (TSW1200EVM), available through TI, consists of a circuit board and a set of preconfigured design files, which enable designers to prototype and evaluate the performance of the latest high-speed ADCs featuring serialized LVDS outputs. The EVM can be connected to a logic analyzer for data analysis or to TI's TSW1100, a high-speed CMOS data capture and analysis tool.

Built on the Virtex-4 LX25 platform, the Xilinx deserializer reference design accepts up to four simultaneous ADC channels and provides automatic de-skew and clock alignment functions. Each ADC output is serialized and transmitted through a separate LVDS serial pair. An independent frame clock and serial data clock are provided to allow for easy deserialization.

The Xilinx reference design exploits the unique ISERDES dedicated logic in the I/O of the Virtex-4 devices to provide the necessary timing to accept these extremely fast input signals and translate into parallel output busses, which can be more easily integrated, said the company.

The serial LVDS interface provides several distinct benefits to the system designer. The lower pin count, both on the ADC and the FPGA, results in less routing lines, potentially fewer board layers, better immunity to external noise and extremely low crosstalk and injection of noise into the printed-circuit-board, which translate directly into lower system costs and improved system reliability when compared to legacy ADC communication interface technology, said the company.

The pin-compatible ADS6000 family consists of dual- and quad-channel, 12- and 14-bit ADCs at speeds of 80, 100, 125 mega samples per second (MSPS) to provide an upgrade path for customers designing communications, instrumentation and imaging products. The ADS6000 family features signal-to-noise ratio of 73.2 dB dBFS (70.3 dBFS for the 12-bit family) with 83 dBc of spurious free dynamic range at 50 MHZ input frequency while only consuming 420 mW of power per channel at 125 MSPS (330 mW/channel at 80 MSPS). The devices allow high-system density for multi-channel applications.

The Xilinx Virtex-4 family consists of 17 devices and three domain-optimized platforms. The Virtex-4 LX FPGAs are optimized for logic-intensive designs; Virtex-4 FX FPGAs for high-speed serial connectivity and embedded processing, and Virtex-4 SX FPGAs for high-performance signal processing.

Pricing: The TSW1200EVM high-speed ADC LVDS evaluation module can be purchased directly through TI and its distributors for $649.
Availability: The reference design (including VHDL code and test files) and application note are available free of charge from the Xilinx web site.
Product information: reference design app notes, TI ADS6000 data converters, and Virtex-4 products

Xilinx Inc. , 1-408-559-7778,

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