The last major functional block of the Z meter is one that has been monolithically integrated for decades: the digital voltmeter (DVM). In older Z meters, this was often the Intersil or Maxim 7106, a dual-slope auto-zeroing 40-pin DIP IC. Over the course of time, preferred methods of ADC conversion have emerged. Dual-slope schemes are not among them, because their voltage ramps must maintain linearity over a wide range of amplitudes. Near zero-scale, the amplitude of the dual-ramp waveform is very small and leads to various difficulties.
The preferred method is now the delta-sigma (Δ-Σ) converter — and there are some good reasons why. First, like resistive-ladder-based ADCs, there are no missing codes or nonmonotonicity. Like op-amps, they maintain a kind of virtual-ground input that limits the requirement for linear range to near-zero. Like other integrating schemes, the longer you wait, the more resolution you get.
The resolution and the full-scale count can be traded off digitally for different measurement rates using DSP techniques of decimation and interpolation. Therefore, the DVM should use a Δ-Σ converter of some kind. Monolithic variations on them exist in the marketplace, and this block in the Z meter IC design can be considered as essentially finished.
So where does this leave us? In this series, we have gone through all the functional subsystem blocks of circuitry that are needed to make a Z meter. None of them pose any formidable integration challenges and for Z meters, no high-speed processes are even needed. (However, with them, the measurement range and accuracy of the meter can be extended, and Z analyzers can then be considered.)
Various combinations of different kinds of blocks lead to many possible Z meter designs. Which schemes are preferred for a given function depends significantly on the designer. Those who excel at precision analog design might use a translinear multiplier for phase detection. These multipliers can be very fast and accurate. Others who like switched-capacitor circuits might opt for switch multipliers.
Generators are of particular interest because both analog oscillators and digital synthesizers are feasible. A maximally digital meter would generate sine and cosine waveforms using the very quick methods of incremental function generation in μC firmware and output them to DACs, which drive not only the bridge amplifier, but also the phase detector.
Or the phase detection could be implemented with counter-timer circuits in the time domain, reducing the Z meter to a minimum of analog circuitry. However, analog still has some advantages, and analog amplifiers off the bridge circuit are still required and must have some speed and precision. PLLs generate continuous waveforms with small phase error and analog oscillators are free of the quantization noise of DACs.
A Z meter IC pinout
We now come to that anticipated moment of design in the series when we envisage what the pinout of a Z meter IC might be. One proposal is shown below in a 20-pin DIP or SOIC (or smaller, if you insist). The ±5V supplies consume three pins, plus a fourth for separated analog and supply grounds. Two are needed for the input (pins 5 and 6), with another pin for the guard lead (that's pin 7) — a simple Z meter refinement not covered in this series.
Preferably, four pins would be used, two for drive and two for sense. That would force us to use a 24-pin package, which is not much larger. Three additional pins make available key voltages: the amplified bridge voltages and vo , as input to the DVM, which gives the option of not including the DVM on the chip; some μCs have ADCs that are good enough. The two bridge voltage pins could be traded in for two bridge sense pins. The four-terminal probing of Zx can occur in a 20-pin package, albeit with less observability within the Z meter.
The remaining pins, other than the serial 3-wire μC interface, are for external capacitors: two for the phase detector low-pass filters, two for the Wien-bridge oscillator, one for amplitude peak detection, and one for the ADC integrator. These capacitors have relatively large values. Although, by using capacitance multipliers on-chip they too could be eliminated, because none of them require small-tolerance values. The only requirement is that they remain stable for a few cycles of the oscillator waveform. Perhaps with some further design intensity, a 16-pin Z meter could be realized.
This series has not covered some of the additional, finer points in designing an actual Z meter. Stray lead impedance and the problems caused by it can be minimized. Lead series resistance is removed from measurement by using four-terminal sensing. (The B&K 875A has two leads, and senses lead current to compensate for voltage drop in the leads.) Lead inductance (including mutual inductance) can be minimized without significantly impacting Z meter IC design. Stray capacitance across the Zx input terminals can also be compensated for with monolithic circuits.
Another minor embellishment is the real component associated with capacitance. I had not embellished the basic bridge equations to bring this out, but for capacitance measurement, the resulting real component that the phase detector outputs can easily be shown to be the parallel conductance across the capacitor, not the series resistance. (Both real and reactive components for capacitance measurement are measured as i/v.)
However, a shunt GC model can be converted to a series RC model and is another good application for translinear circuits, because a squaring function is required. While precision timing and low-leakage applications using capacitors might require measurement of Gp , capacitor series resistance is more commonly desired, and is of interest in power electronics designs.
The Z meter is a good choice for an integrated instrument because it has fewer design risks than some other kinds of instruments. Yet no commercial IC exists as a single-chip Z meter.
As a postscript, I have several Z meter concepts that I am developing. The first starts from the semi-obsolete B&K 875A design and uses its basic functional blocks, with refinements. Another is maximally μC and is a low-cost two-chip solution. A third uses a digital generator and analog phase detection. Another is a VFC-based Z meter. All have commercial-grade specifications.
I hope that this series gives both instrument makers and IC companies something to ponder for new product possibilities. While various details have been omitted from this article series for the sake of brevity, I have tried to present enough circuit detail to illustrate the feasibility of a monolithic Z meter to those seriously interested. If you decide to start a design project, possibly encouraged by this series, I would not mind being involved, and am available in a technical advisory capacity. I would like to see a monolithic Z meter, and see it done right.
Besides Z meters, Z analyzers, two-port analyzers (curve tracers), and pulse, function, and waveform generators are candidates for integration. So is, to a significant extent, the oscilloscope of motion-control instruments, the benchtop dynamometer. I have been busy working out the design details and building prototypes of all of these categories of instruments for eventual integration.
- Z Meter on a Chip? Impedance Meter Phase Detectors
- Z Meter on a Chip? Impedance Meter Oscillators
- Z Meter on a Chip? Impedance Meter Range Capabilities
- Z Meter on a Chip? Impedance Meter Bridge Circuits
- An Instrument on a Chip? The Minimum-Subsystem Instrument
- An Instrument on a Chip? The Configuration Problem
- An Instrument on a Chip? Some Emerging Instruments & the China Factor
- An Instrument on a Chip? A Look Back
- Thermocouple Nodules, Cold Junctions & Integration Opportunities